1. Field of the Invention
The present invention relates to a semiconductor device having a boundary scan test circuit and, more particularly, to an improvement on data registers in a boundary scan test circuit of a semiconductor integrated circuit.
2. Description of the Related Art
In a test for semiconductor devices which are fabricated by using advanced technology such as surface mounting, tape automated bonding, a multichip module and a complicated ASIC, there is a problem that all nodes of each IC tip mounted on the circuit board or molded in a package cannot be tested by a conventional test using an IC tester.
A boundary scan test is one of methods for determining whether or not a semiconductor device mounted on a circuit board is suitably fabricated. The boundary scan test is used to examine that each of designated IC chips is properly mounted on a circuit board, that all connection pins of each IC chip are properly connected to corresponding terminal of the circuit board, and that an internal logic circuit of each IC chip provides a predetermined function.
FIG. 1 is a schematic perspective view showing the structure of a semiconductor device in which a boundary scan test is carried out. As shown in this drawing, the semiconductor device is provided with connection pins composed of input pins 53 and output pins 53a. Boundary scan register cells 31 on the input side are disposed between the input pins 53 and an internal logic circuit 38, while boundary scan register cells 31a on the output side are disposed between the internal logic circuit 38 and the output pins 53a. In an ordinary (normal) operation mode, each of the register cells 31 transmits input data from associated one of the input pins to the internal logic circuit 38 as it is, while each of the register cells 31a transmits output data obtained from the internal logic circuit 38 to associated one of the output pins 53a as it is.
All of the boundary scan register cells 31 and 31a form a single shift register 60 when serially connected to each other as shown in FIG. 1. Resulting from such a construction, in a test operation mode, a set of test signals are input through a test data input terminal TDI or directly input to input pins 53 in accordance with one of the test operation modes, and then supplied to the internal logic circuit 38. Also, test data from the internal logic circuit 38 are output through a test data output terminal TDO or are directly output from output pins 53a. Other than the register cells 31 and 31a, there are provided an identification (ID) code register 32, a bypass register 33 and an instruction register 34.
In a semiconductor device having the boundary scan test circuit as described above, it is necessary to provide a large number of registers for the boundary scan test circuit, resulting in a larger chip area of the semiconductor device although it is requested to have a smaller chip area.
In view of the foregoing, an object of the present invention is to provide a boundary scan test circuit for a semiconductor device in which a reduced number of registers for the boundary scan test circuit is provided, thereby obtaining a reduced chip area for the semiconductor device.
In accordance with the present invention, there is provided a semiconductor device comprising an internal logic circuit, a plurality of external pins and a boundary scan test circuit including a plurality of boundary scan register cells each disposed correspondingly to associated one of the external pins for transmitting parallel data between the internal logic circuit and associated one of the external pins, the boundary scan register cells being electrically connected to each other responsive to an external signal to form a shift register for transmitting serial data.
In a first aspect of the present invention, each of the boundary scan register cells in the boundary scan test circuit comprises: a first selector having a first input for inputting the parallel data, a second input for inputting the serial data and a third input for inputting a code signal representing a bit of an ID code of the semiconductor device, the first selector selecting one of the parallel data, serial data and code signal in accordance with an input switching signal; a first register for latching an output signal from the first selector in response to a first latch signal; a second register for latching an output signal from the first register in response to a second latch signal; and a second selector for selecting the parallel data or an output signal from the second register in accordance with an output switching signal, an output signal from the first register of one of the boundary scan register cells constituting the serial data to be input to succeeding one of the boundary scan register cells when the boundary scan register cells are connected to form the shift register. The third input of the first selector is preferably maintained at a first potential or a second potential in accordance with the bit of the ID code.
In a second aspect of the present invention, each of the register cells in the boundary scan test circuit comprises a first selector for selecting one of the parallel data and the serial data in accordance with an input switching signal; a first register for latching an output signal from the first selector in response to a first latch signal, the first register further being set or reset in accordance with a code signal representing a bit of an ID code of the semiconductor device in response to a second external signal; a second register for latching an output signal from the first register in response to a second latch signal; and a second selecting circuit for selecting the parallel data or an output signal from the second register in accordance with an output switching signal, an output signal from the first register of one of the boundary scan register cells constituting the serial data to be input to succeeding one of the boundary scan register cells when the boundary scan register cells are connected to form the shift register.
With the semiconductor device according to the present invention, in a test operation mode, parallel data, serial data, or a code signal representing a bit of an identification code of the semiconductor device is selected by the first selector in each of boundary scan register cells constituting a shift register when coupled together, thereby making it possible to transmit a test data by the shift register in the test operation mode, while parallel data input in the normal operation mode can be supplied to the internal logic circuit or the connection pins. Further, the code signal representing a bit of an ID code of the semiconductor device is output directly from each of the boundary scan register cells, so that the ID code can be read out from the shift register. Hence, it is not necessary to include in a boundary scan register cell an identification code register for storing the code signal of the semiconductor device. Accordingly, it is possible to simplify the structure of a semiconductor device having a boundary scan test circuit, thereby reducing the chip area of the semiconductor device.